tests/test-bitrotate.c

   1 /* Test of <bitrotate.h> substitute.
   2    Copyright (C) 2007-2024 Free Software Foundation, Inc.
   3
   4    This program is free software: you can redistribute it and/or modify
   5    it under the terms of the GNU General Public License as published by
   6    the Free Software Foundation, either version 3 of the License, or
   7    (at your option) any later version.
   8
   9    This program is distributed in the hope that it will be useful,
  10    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12    GNU General Public License for more details.
  13
  14    You should have received a copy of the GNU General Public License
  15    along with this program.  If not, see <https://www.gnu.org/licenses/>.  */
  16
  17 /* Written by Simon Josefsson <simon@josefsson.org>, 2008.  */
  18
  19 #include <config.h>
  20
  21 #include "bitrotate.h"
  22
  23 #include "macros.h"
  24
  25 int
  26 main (void)
  27 {
  28   ASSERT (rotl8 (42, 0) == 42);
  29   ASSERT (rotl8 (42, 1) == 84);
  30   ASSERT (rotl8 (42, 2) == 168);
  31   ASSERT (rotl8 (42, 3) == 81);
  32   ASSERT (rotl8 (42, 4) == 162);
  33   ASSERT (rotl8 (42, 5) == 69);
  34   ASSERT (rotl8 (42, 6) == 138);
  35   ASSERT (rotl8 (42, 7) == 21);
  36   ASSERT (rotl8 (42, 8) == 42);
  37
  38   ASSERT (rotr8 (42, 0) == 42);
  39   ASSERT (rotr8 (42, 1) == 21);
  40   ASSERT (rotr8 (42, 2) == 138);
  41   ASSERT (rotr8 (42, 3) == 69);
  42   ASSERT (rotr8 (42, 4) == 162);
  43   ASSERT (rotr8 (42, 5) == 81);
  44   ASSERT (rotr8 (42, 6) == 168);
  45   ASSERT (rotr8 (42, 7) == 84);
  46   ASSERT (rotr8 (42, 8) == 42);
  47
  48   ASSERT (rotl16 (43981, 0) == 43981);
  49   ASSERT (rotl16 (43981, 1) == 22427);
  50   ASSERT (rotl16 (43981, 2) == 44854);
  51   ASSERT (rotl16 (43981, 3) == 24173);
  52   ASSERT (rotl16 (43981, 4) == 48346);
  53   ASSERT (rotl16 (43981, 5) == 31157);
  54   ASSERT (rotl16 (43981, 6) == 62314);
  55   ASSERT (rotl16 (43981, 7) == 59093);
  56   ASSERT (rotl16 (43981, 8) == 52651);
  57   ASSERT (rotl16 (43981, 9) == 39767);
  58   ASSERT (rotl16 (43981, 10) == 13999);
  59   ASSERT (rotl16 (43981, 11) == 27998);
  60   ASSERT (rotl16 (43981, 12) == 55996);
  61   ASSERT (rotl16 (43981, 13) == 46457);
  62   ASSERT (rotl16 (43981, 14) == 27379);
  63   ASSERT (rotl16 (43981, 15) == 54758);
  64   ASSERT (rotl16 (43981, 16) == 43981);
  65
  66   ASSERT (rotr16 (43981, 0) == 43981);
  67   ASSERT (rotr16 (43981, 1) == 54758);
  68   ASSERT (rotr16 (43981, 2) == 27379);
  69   ASSERT (rotr16 (43981, 3) == 46457);
  70   ASSERT (rotr16 (43981, 4) == 55996);
  71   ASSERT (rotr16 (43981, 5) == 27998);
  72   ASSERT (rotr16 (43981, 6) == 13999);
  73   ASSERT (rotr16 (43981, 7) == 39767);
  74   ASSERT (rotr16 (43981, 8) == 52651);
  75   ASSERT (rotr16 (43981, 9) == 59093);
  76   ASSERT (rotr16 (43981, 10) == 62314);
  77   ASSERT (rotr16 (43981, 11) == 31157);
  78   ASSERT (rotr16 (43981, 12) == 48346);
  79   ASSERT (rotr16 (43981, 13) == 24173);
  80   ASSERT (rotr16 (43981, 14) == 44854);
  81   ASSERT (rotr16 (43981, 15) == 22427);
  82   ASSERT (rotr16 (43981, 16) == 43981);
  83
  84   ASSERT (rotl32 (2309737967U, 1) == 324508639U);
  85   ASSERT (rotl32 (2309737967U, 2) == 649017278U);
  86   ASSERT (rotl32 (2309737967U, 3) == 1298034556U);
  87   ASSERT (rotl32 (2309737967U, 4) == 2596069112U);
  88   ASSERT (rotl32 (2309737967U, 5) == 897170929U);
  89   ASSERT (rotl32 (2309737967U, 6) == 1794341858U);
  90   ASSERT (rotl32 (2309737967U, 7) == 3588683716U);
  91   ASSERT (rotl32 (2309737967U, 8) == 2882400137U);
  92   ASSERT (rotl32 (2309737967U, 9) == 1469832979U);
  93   ASSERT (rotl32 (2309737967U, 10) == 2939665958U);
  94   ASSERT (rotl32 (2309737967U, 11) == 1584364621U);
  95   ASSERT (rotl32 (2309737967U, 12) == 3168729242U);
  96   ASSERT (rotl32 (2309737967U, 13) == 2042491189U);
  97   ASSERT (rotl32 (2309737967U, 14) == 4084982378U);
  98   ASSERT (rotl32 (2309737967U, 15) == 3874997461U);
  99   ASSERT (rotl32 (2309737967U, 16) == 3455027627U);
 100   ASSERT (rotl32 (2309737967U, 17) == 2615087959U);
 101   ASSERT (rotl32 (2309737967U, 18) == 935208623U);
 102   ASSERT (rotl32 (2309737967U, 19) == 1870417246U);
 103   ASSERT (rotl32 (2309737967U, 20) == 3740834492U);
 104   ASSERT (rotl32 (2309737967U, 21) == 3186701689U);
 105   ASSERT (rotl32 (2309737967U, 22) == 2078436083U);
 106   ASSERT (rotl32 (2309737967U, 23) == 4156872166U);
 107   ASSERT (rotl32 (2309737967U, 24) == 4018777037U);
 108   ASSERT (rotl32 (2309737967U, 25) == 3742586779U);
 109   ASSERT (rotl32 (2309737967U, 26) == 3190206263U);
 110   ASSERT (rotl32 (2309737967U, 27) == 2085445231U);
 111   ASSERT (rotl32 (2309737967U, 28) == 4170890462U);
 112   ASSERT (rotl32 (2309737967U, 29) == 4046813629U);
 113   ASSERT (rotl32 (2309737967U, 30) == 3798659963U);
 114   ASSERT (rotl32 (2309737967U, 31) == 3302352631U);
 115
 116   ASSERT (rotr32 (2309737967U, 1) == 3302352631lU);
 117   ASSERT (rotr32 (2309737967U, 2) == 3798659963lU);
 118   ASSERT (rotr32 (2309737967U, 3) == 4046813629lU);
 119   ASSERT (rotr32 (2309737967U, 4) == 4170890462lU);
 120   ASSERT (rotr32 (2309737967U, 5) == 2085445231lU);
 121   ASSERT (rotr32 (2309737967U, 6) == 3190206263lU);
 122   ASSERT (rotr32 (2309737967U, 7) == 3742586779lU);
 123   ASSERT (rotr32 (2309737967U, 8) == 4018777037lU);
 124   ASSERT (rotr32 (2309737967U, 9) == 4156872166lU);
 125   ASSERT (rotr32 (2309737967U, 10) == 2078436083lU);
 126   ASSERT (rotr32 (2309737967U, 11) == 3186701689lU);
 127   ASSERT (rotr32 (2309737967U, 12) == 3740834492lU);
 128   ASSERT (rotr32 (2309737967U, 13) == 1870417246lU);
 129   ASSERT (rotr32 (2309737967U, 14) == 935208623lU);
 130   ASSERT (rotr32 (2309737967U, 15) == 2615087959lU);
 131   ASSERT (rotr32 (2309737967U, 16) == 3455027627lU);
 132   ASSERT (rotr32 (2309737967U, 17) == 3874997461lU);
 133   ASSERT (rotr32 (2309737967U, 18) == 4084982378lU);
 134   ASSERT (rotr32 (2309737967U, 19) == 2042491189lU);
 135   ASSERT (rotr32 (2309737967U, 20) == 3168729242lU);
 136   ASSERT (rotr32 (2309737967U, 21) == 1584364621lU);
 137   ASSERT (rotr32 (2309737967U, 22) == 2939665958lU);
 138   ASSERT (rotr32 (2309737967U, 23) == 1469832979lU);
 139   ASSERT (rotr32 (2309737967U, 24) == 2882400137lU);
 140   ASSERT (rotr32 (2309737967U, 25) == 3588683716lU);
 141   ASSERT (rotr32 (2309737967U, 26) == 1794341858lU);
 142   ASSERT (rotr32 (2309737967U, 27) == 897170929lU);
 143   ASSERT (rotr32 (2309737967U, 28) == 2596069112lU);
 144   ASSERT (rotr32 (2309737967U, 29) == 1298034556lU);
 145   ASSERT (rotr32 (2309737967U, 30) == 649017278lU);
 146   ASSERT (rotr32 (2309737967U, 31) == 324508639lU);
 147
 148 #ifdef UINT64_MAX
 149   ASSERT (rotl64 (16045690984503098046ULL, 1) == 13644637895296644477ULL);
 150   ASSERT (rotl64 (16045690984503098046ULL, 2) == 8842531716883737339ULL);
 151   ASSERT (rotl64 (16045690984503098046ULL, 3) == 17685063433767474678ULL);
 152   ASSERT (rotl64 (16045690984503098046ULL, 4) == 16923382793825397741ULL);
 153   ASSERT (rotl64 (16045690984503098046ULL, 5) == 15400021513941243867ULL);
 154   ASSERT (rotl64 (16045690984503098046ULL, 6) == 12353298954172936119ULL);
 155   ASSERT (rotl64 (16045690984503098046ULL, 7) == 6259853834636320623ULL);
 156   ASSERT (rotl64 (16045690984503098046ULL, 8) == 12519707669272641246ULL);
 157   ASSERT (rotl64 (16045690984503098046ULL, 9) == 6592671264835730877ULL);
 158   ASSERT (rotl64 (16045690984503098046ULL, 10) == 13185342529671461754ULL);
 159   ASSERT (rotl64 (16045690984503098046ULL, 11) == 7923940985633371893ULL);
 160   ASSERT (rotl64 (16045690984503098046ULL, 12) == 15847881971266743786ULL);
 161   ASSERT (rotl64 (16045690984503098046ULL, 13) == 13249019868823935957ULL);
 162   ASSERT (rotl64 (16045690984503098046ULL, 14) == 8051295663938320299ULL);
 163   ASSERT (rotl64 (16045690984503098046ULL, 15) == 16102591327876640598ULL);
 164   ASSERT (rotl64 (16045690984503098046ULL, 16) == 13758438582043729581ULL);
 165   ASSERT (rotl64 (16045690984503098046ULL, 17) == 9070133090377907547ULL);
 166   ASSERT (rotl64 (16045690984503098046ULL, 18) == 18140266180755815094ULL);
 167   ASSERT (rotl64 (16045690984503098046ULL, 19) == 17833788287802078573ULL);
 168   ASSERT (rotl64 (16045690984503098046ULL, 20) == 17220832501894605531ULL);
 169   ASSERT (rotl64 (16045690984503098046ULL, 21) == 15994920930079659447ULL);
 170   ASSERT (rotl64 (16045690984503098046ULL, 22) == 13543097786449767279ULL);
 171   ASSERT (rotl64 (16045690984503098046ULL, 23) == 8639451499189982943ULL);
 172   ASSERT (rotl64 (16045690984503098046ULL, 24) == 17278902998379965886ULL);
 173   ASSERT (rotl64 (16045690984503098046ULL, 25) == 16111061923050380157ULL);
 174   ASSERT (rotl64 (16045690984503098046ULL, 26) == 13775379772391208699ULL);
 175   ASSERT (rotl64 (16045690984503098046ULL, 27) == 9104015471072865783ULL);
 176   ASSERT (rotl64 (16045690984503098046ULL, 28) == 18208030942145731566ULL);
 177   ASSERT (rotl64 (16045690984503098046ULL, 29) == 17969317810581911517ULL);
 178   ASSERT (rotl64 (16045690984503098046ULL, 30) == 17491891547454271419ULL);
 179   ASSERT (rotl64 (16045690984503098046ULL, 31) == 16537039021198991223ULL);
 180   ASSERT (rotl64 (16045690984503098046ULL, 32) == 14627333968688430831ULL);
 181   ASSERT (rotl64 (16045690984503098046ULL, 33) == 10807923863667310047ULL);
 182   ASSERT (rotl64 (16045690984503098046ULL, 34) == 3169103653625068479ULL);
 183   ASSERT (rotl64 (16045690984503098046ULL, 35) == 6338207307250136958ULL);
 184   ASSERT (rotl64 (16045690984503098046ULL, 36) == 12676414614500273916ULL);
 185   ASSERT (rotl64 (16045690984503098046ULL, 37) == 6906085155290996217ULL);
 186   ASSERT (rotl64 (16045690984503098046ULL, 38) == 13812170310581992434ULL);
 187   ASSERT (rotl64 (16045690984503098046ULL, 39) == 9177596547454433253ULL);
 188   ASSERT (rotl64 (16045690984503098046ULL, 40) == 18355193094908866506ULL);
 189   ASSERT (rotl64 (16045690984503098046ULL, 41) == 18263642116108181397ULL);
 190   ASSERT (rotl64 (16045690984503098046ULL, 42) == 18080540158506811179ULL);
 191   ASSERT (rotl64 (16045690984503098046ULL, 43) == 17714336243304070743ULL);
 192   ASSERT (rotl64 (16045690984503098046ULL, 44) == 16981928412898589871ULL);
 193   ASSERT (rotl64 (16045690984503098046ULL, 45) == 15517112752087628127ULL);
 194   ASSERT (rotl64 (16045690984503098046ULL, 46) == 12587481430465704639ULL);
 195   ASSERT (rotl64 (16045690984503098046ULL, 47) == 6728218787221857663ULL);
 196   ASSERT (rotl64 (16045690984503098046ULL, 48) == 13456437574443715326ULL);
 197   ASSERT (rotl64 (16045690984503098046ULL, 49) == 8466131075177879037ULL);
 198   ASSERT (rotl64 (16045690984503098046ULL, 50) == 16932262150355758074ULL);
 199   ASSERT (rotl64 (16045690984503098046ULL, 51) == 15417780227001964533ULL);
 200   ASSERT (rotl64 (16045690984503098046ULL, 52) == 12388816380294377451ULL);
 201   ASSERT (rotl64 (16045690984503098046ULL, 53) == 6330888686879203287ULL);
 202   ASSERT (rotl64 (16045690984503098046ULL, 54) == 12661777373758406574ULL);
 203   ASSERT (rotl64 (16045690984503098046ULL, 55) == 6876810673807261533ULL);
 204   ASSERT (rotl64 (16045690984503098046ULL, 56) == 13753621347614523066ULL);
 205   ASSERT (rotl64 (16045690984503098046ULL, 57) == 9060498621519494517ULL);
 206   ASSERT (rotl64 (16045690984503098046ULL, 58) == 18120997243038989034ULL);
 207   ASSERT (rotl64 (16045690984503098046ULL, 59) == 17795250412368426453ULL);
 208   ASSERT (rotl64 (16045690984503098046ULL, 60) == 17143756751027301291ULL);
 209   ASSERT (rotl64 (16045690984503098046ULL, 61) == 15840769428345050967ULL);
 210   ASSERT (rotl64 (16045690984503098046ULL, 62) == 13234794782980550319ULL);
 211   ASSERT (rotl64 (16045690984503098046ULL, 63) == 8022845492251549023ULL);
 212
 213   ASSERT (rotr64 (16045690984503098046ULL, 1) == 8022845492251549023ULL);
 214   ASSERT (rotr64 (16045690984503098046ULL, 2) == 13234794782980550319ULL);
 215   ASSERT (rotr64 (16045690984503098046ULL, 3) == 15840769428345050967ULL);
 216   ASSERT (rotr64 (16045690984503098046ULL, 4) == 17143756751027301291ULL);
 217   ASSERT (rotr64 (16045690984503098046ULL, 5) == 17795250412368426453ULL);
 218   ASSERT (rotr64 (16045690984503098046ULL, 6) == 18120997243038989034ULL);
 219   ASSERT (rotr64 (16045690984503098046ULL, 7) == 9060498621519494517ULL);
 220   ASSERT (rotr64 (16045690984503098046ULL, 8) == 13753621347614523066ULL);
 221   ASSERT (rotr64 (16045690984503098046ULL, 9) == 6876810673807261533ULL);
 222   ASSERT (rotr64 (16045690984503098046ULL, 10) == 12661777373758406574ULL);
 223   ASSERT (rotr64 (16045690984503098046ULL, 11) == 6330888686879203287ULL);
 224   ASSERT (rotr64 (16045690984503098046ULL, 12) == 12388816380294377451ULL);
 225   ASSERT (rotr64 (16045690984503098046ULL, 13) == 15417780227001964533ULL);
 226   ASSERT (rotr64 (16045690984503098046ULL, 14) == 16932262150355758074ULL);
 227   ASSERT (rotr64 (16045690984503098046ULL, 15) == 8466131075177879037ULL);
 228   ASSERT (rotr64 (16045690984503098046ULL, 16) == 13456437574443715326ULL);
 229   ASSERT (rotr64 (16045690984503098046ULL, 17) == 6728218787221857663ULL);
 230   ASSERT (rotr64 (16045690984503098046ULL, 18) == 12587481430465704639ULL);
 231   ASSERT (rotr64 (16045690984503098046ULL, 19) == 15517112752087628127ULL);
 232   ASSERT (rotr64 (16045690984503098046ULL, 20) == 16981928412898589871ULL);
 233   ASSERT (rotr64 (16045690984503098046ULL, 21) == 17714336243304070743ULL);
 234   ASSERT (rotr64 (16045690984503098046ULL, 22) == 18080540158506811179ULL);
 235   ASSERT (rotr64 (16045690984503098046ULL, 23) == 18263642116108181397ULL);
 236   ASSERT (rotr64 (16045690984503098046ULL, 24) == 18355193094908866506ULL);
 237   ASSERT (rotr64 (16045690984503098046ULL, 25) == 9177596547454433253ULL);
 238   ASSERT (rotr64 (16045690984503098046ULL, 26) == 13812170310581992434ULL);
 239   ASSERT (rotr64 (16045690984503098046ULL, 27) == 6906085155290996217ULL);
 240   ASSERT (rotr64 (16045690984503098046ULL, 28) == 12676414614500273916ULL);
 241   ASSERT (rotr64 (16045690984503098046ULL, 29) == 6338207307250136958ULL);
 242   ASSERT (rotr64 (16045690984503098046ULL, 30) == 3169103653625068479ULL);
 243   ASSERT (rotr64 (16045690984503098046ULL, 31) == 10807923863667310047ULL);
 244   ASSERT (rotr64 (16045690984503098046ULL, 32) == 14627333968688430831ULL);
 245   ASSERT (rotr64 (16045690984503098046ULL, 33) == 16537039021198991223ULL);
 246   ASSERT (rotr64 (16045690984503098046ULL, 34) == 17491891547454271419ULL);
 247   ASSERT (rotr64 (16045690984503098046ULL, 35) == 17969317810581911517ULL);
 248   ASSERT (rotr64 (16045690984503098046ULL, 36) == 18208030942145731566ULL);
 249   ASSERT (rotr64 (16045690984503098046ULL, 37) == 9104015471072865783ULL);
 250   ASSERT (rotr64 (16045690984503098046ULL, 38) == 13775379772391208699ULL);
 251   ASSERT (rotr64 (16045690984503098046ULL, 39) == 16111061923050380157ULL);
 252   ASSERT (rotr64 (16045690984503098046ULL, 40) == 17278902998379965886ULL);
 253   ASSERT (rotr64 (16045690984503098046ULL, 41) == 8639451499189982943ULL);
 254   ASSERT (rotr64 (16045690984503098046ULL, 42) == 13543097786449767279ULL);
 255   ASSERT (rotr64 (16045690984503098046ULL, 43) == 15994920930079659447ULL);
 256   ASSERT (rotr64 (16045690984503098046ULL, 44) == 17220832501894605531ULL);
 257   ASSERT (rotr64 (16045690984503098046ULL, 45) == 17833788287802078573ULL);
 258   ASSERT (rotr64 (16045690984503098046ULL, 46) == 18140266180755815094ULL);
 259   ASSERT (rotr64 (16045690984503098046ULL, 47) == 9070133090377907547ULL);
 260   ASSERT (rotr64 (16045690984503098046ULL, 48) == 13758438582043729581ULL);
 261   ASSERT (rotr64 (16045690984503098046ULL, 49) == 16102591327876640598ULL);
 262   ASSERT (rotr64 (16045690984503098046ULL, 50) == 8051295663938320299ULL);
 263   ASSERT (rotr64 (16045690984503098046ULL, 51) == 13249019868823935957ULL);
 264   ASSERT (rotr64 (16045690984503098046ULL, 52) == 15847881971266743786ULL);
 265   ASSERT (rotr64 (16045690984503098046ULL, 53) == 7923940985633371893ULL);
 266   ASSERT (rotr64 (16045690984503098046ULL, 54) == 13185342529671461754ULL);
 267   ASSERT (rotr64 (16045690984503098046ULL, 55) == 6592671264835730877ULL);
 268   ASSERT (rotr64 (16045690984503098046ULL, 56) == 12519707669272641246ULL);
 269   ASSERT (rotr64 (16045690984503098046ULL, 57) == 6259853834636320623ULL);
 270   ASSERT (rotr64 (16045690984503098046ULL, 58) == 12353298954172936119ULL);
 271   ASSERT (rotr64 (16045690984503098046ULL, 59) == 15400021513941243867ULL);
 272   ASSERT (rotr64 (16045690984503098046ULL, 60) == 16923382793825397741ULL);
 273   ASSERT (rotr64 (16045690984503098046ULL, 61) == 17685063433767474678ULL);
 274   ASSERT (rotr64 (16045690984503098046ULL, 62) == 8842531716883737339ULL);
 275   ASSERT (rotr64 (16045690984503098046ULL, 63) == 13644637895296644477ULL);
 276 #endif /* UINT64_MAX */
 277
 278   return test_exit_status;
 279 }