accumulator.vhd

   1 library ieee;
   2     use ieee.std_logic_1164.all;
   3     use ieee.numeric_std.all;
   4
   5 entity accumulator is
   6     port (
   7         rst     : in  std_logic;
   8         clk     : in  std_logic;
   9         a       : in  std_logic_vector(3 downto 0);
  10         accum   : out std_logic_vector(3 downto 0)
  11     );
  12 end accumulator;
  13
  14 architecture rtl of accumulator is
  15
  16 signal accumL: unsigned(3 downto 0);
  17
  18 begin
  19
  20     accumulate: process (clk, rst) begin
  21     if (rst = '1') then
  22         accumL <= "0000";
  23     elsif (clk'event and clk= '1') then
  24         accumL <= accumL + to_unsigned(a);
  25     end if;
  26     end process;
  27
  28     accum <= std_logic_vector(accumL);
  29
  30 end rtl;