add ram dual and single port
[vhdl_digital_base_blocks.git] / debounce_pkg.vhd
blob6aa2890edcf67634b7629f9455bc8adf18802ba7
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
6 package debounce_pkg is
8 -------------------------------------------------------------------------
9 -- Clock definitions
10 -------------------------------------------------------------------------
11 constant SYS_FREQ : natural := 100_000; -- Clock freq. in kHz
12 constant SYS_PERIOD : natural := 1_000_000/SYS_FREQ; -- In nanosec., 10 nsec for 100MHz clock
13 constant DIV_DEB : natural := 500_000/SYS_PERIOD; -- Clock divider for 500us from 100MHz
14 constant DIV_DEB_W : natural := integer(ceil(log2(real(DIV_DEB+1))));
17 -------------------------------------------------------------------------
18 -- Size definitions
19 -------------------------------------------------------------------------
20 constant DEB_LEN : natural := 32;
21 constant DEB_LEN_W : natural := integer(ceil(log2(real(DEB_LEN+1))));
22 constant DEB_THRES_LO : natural := DEB_LEN/10;
23 constant DEB_THRES_HI : natural := 9*DEB_LEN/10;
25 end debounce_pkg;