add ram dual and single port
[vhdl_digital_base_blocks.git] / pwm_reg_pack.vhd
blob1c242ba31ca438d9b1b359c8a945697904015bf2
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
6 package pwm_reg_pack is
8 -------------------------------------------------------------------------
9 -- Data size definitions
10 -------------------------------------------------------------------------
11 constant SYS_CLK : natural := 100_000; -- System clock in kHz
12 constant PWM_CLK : natural := 500; -- PWM clock in kHz
13 constant DUTY_CYCLE_W : natural := 5; -- PWM resolution in bits
14 constant PERIOD : natural := SYS_CLK / (PWM_CLK * 2**DUTY_CYCLE_W);
15 constant PERIOD_W : natural := integer(ceil(log2(real(PERIOD+1))));
17 end pwm_reg_pack;