ram_single_port.vhd

   1 library ieee;
   2     use ieee.std_logic_1164.all;
   3     use ieee.std_logic_unsigned.all;
   4
   5 entity ram_single_port is
   6 generic (
   7     addr_width : natural := 9; --512x8
   8     data_width : natural := 8
   9     );
  10 port (
  11     addr            : in  std_logic_vector (addr_width - 1 downto 0);
  12     write_en        : in  std_logic;
  13     clk             : in  std_logic;
  14     din             : in  std_logic_vector (data_width - 1 downto 0);
  15     dout            : out std_logic_vector (data_width - 1 downto 0)
  16   );
  17 end ram_single_port;
  18
  19 architecture rtl of ram_single_port is
  20
  21     type mem_type is array ((2** addr_width) - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
  22     signal mem : mem_type;
  23
  24 begin
  25     process (clk)
  26     begin
  27         if (rising_edge(clk)) then
  28             if (write_en = '1') then
  29                 mem(conv_integer(addr)) <= din;
  30             end if;
  31             dout <= mem(conv_integer(addr));
  32         end if;      -- Output register controlled by clock.
  33     end process;
  34 end rtl;